1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device including stacked capacitors, and more particularly to a method for fabricating a semiconductor device including stacked capacitors, in which dummy plate electrodes and charge storage electrodes are formed at a region other than a memory cell region, to control a topology resulting from capacitors, thereby allowing fine interconnection lines to be formed after the formation of those capacitors.
2. Description of the Related Art
As well known, the recent trend to fabricate a semiconductor device with a high degree of integration inevitably results in a reduced cell size. In order to obtain a desired capacitance in the reduced cell size, such a semiconductor device tends to have a stacked capacitor structure having an increased stack height. Such a semiconductor device also tends to have a highly integrated logic circuit arranged around a memory cell region thereof in order to obtain a high performance. For such a highly integrated logic circuit, it is necessary to use interconnection lines of an increased fineness. This also results in an increase in the stack height of capacitors.
Due to such an increased stack height resulting from the manufacture of a semiconductor device with a high integration and high performance, there is a severe topology between a memory cell region formed with capacitors and a logic circuit region around the memory cell region, as shown in FIG. 1. In FIG. 1, the reference character xe2x80x9cAxe2x80x9d denotes the logic circuit region, and the reference character xe2x80x9cBxe2x80x9d denotes the memory cell region.
FIG. 1 is a cross-sectional view illustrating a semiconductor device including stacked capacitors formed in accordance with a conventional method. A semiconductor substrate 1 is first prepared, which is formed with a desired logic circuit in a logic circuit region A, and a plurality of transistors, respectively adapted to drive capacitors to be subsequently formed, in a memory cell region B, as shown in FIG. 1. A nitride or other material is then laminated over the upper surface of the semiconductor substrate 1, thereby forming a first etch barrier film 11. An oxide is subsequently formed over the first etch barrier film (not shown). The oxide film is then planarized to form a first interlayer insulating film 21. The reference numeral xe2x80x9c1xe2x80x9d denotes wells of a first conductivity type, for example, an n-type, xe2x80x9c2xe2x80x9d wells of a second conductivity type, for example, a p-type, xe2x80x9c3xe2x80x9d an element isolation insulating film, xe2x80x9c4xe2x80x9d diffusion regions adapted to be used as source electrodes 4a or drain electrodes 4b, xe2x80x9c5xe2x80x9d a gate oxide film, xe2x80x9c6xe2x80x9d gate electrodes, and xe2x80x9c7xe2x80x9d a first intermediate insulating film.
The first interlayer insulating film 21 and first etch barrier film 11 are then partially removed from the memory cell region B, thereby forming first contact holes through which drain electrodes 4b formed in the memory cell region B are exposed, respectively. Thereafter, a conductive material such as polysilicon is completely filled in the first contact holes. The conductive material remaining on the first interlayer insulating film 21 is then removed using an etchback process. Thus, first contact plugs 31 are formed. The first contact plugs 31, which are arranged at the outermost portion of the memory cell region B adjacent to the logic circuit region A, are dummy plugs. These contact plugs 31, that is, the dummy plugs, will be electrically connected to dummy charge storage electrodes in a subsequent processing step, respectively. Source electrodes 4a formed in the memory cell region B may also be exposed when the drain electrodes 4b are exposed, in order to form contact plugs on those source electrodes 4a. In this case, bit line contacts may be subsequently formed on the contact plugs of the source electrodes 4a. Subsequently, an oxide or other appropriate material is then laminated over the entire upper surface of the resulting structure formed with the contact plugs 31, thereby forming a second interlayer insulating film 22.
Thereafter, the second interlayer insulating film 22, first interlayer insulating film 21, and first etch barrier film 11 are partially removed in a sequential fashion, thereby forming second contact holes through which the source electrodes 4a, in the memory cell region B, to be connected with bit lines in a subsequent processing step, active regions 4 defined in the logic circuit region A to be connected with first interconnection lines, and gate electrodes are exposed. In the case in which contact plugs are also formed on the source electrodes 4a at the processing step of FIG. 1, the second contact holes associated with the bit lines are formed on those contact plugs.
Thereafter, a conductive material is formed over the resulting structure to form a first conductive layer 41 covering the upper surface of the second interlayer insulating film 22 while completely filling the second contact holes. An insulating material is then laminated over the first conductive layer 41, thereby forming a second intermediate insulating film 25. This first conductive layer 41 will be subsequently patterned so that it is used as interconnection lines in the logic circuit region A while being used as bit lines in the memory cell region B. The second intermediate insulating film 25, first conductive layer 41, second interlayer insulating film 22 are then patterned to form first interconnection lines 41a and bit lines 41b. In accordance with the pattering of the second intermediate insulating film 22 at this processing step, respective upper surfaces of the first contact plugs 31 may be exposed. Alternatively, the second interlayer insulating film 22 may be partially left in a small thickness.
A nitride film or other appropriate material film is subsequently laminated over the entire upper surface of the resulting structure, in which the first contact plugs 31 are exposed, thereby forming a second etch barrier film 12. An oxide film is then laminated over the second etch barrier film 12. Then, the oxide film is planarized using a CMP process, thereby forming a third interlayer insulating film 23.
Thereafter, contacts are then formed at the first contact plugs 31 respectively disposed on the drain electrodes 4b to which capacitors are to be connected. The formation of the contacts is achieved by etching the second etch barrier film 12 using a contact mask as an etch barrier, etching the third interlayer insulating film 23 using the contact mask and second etch barrier film 12 as an etch mask, and then etching the second etch barrier film 12. Thereafter, a charge storage electrode material is formed over the upper surface of the resulting structure.
The charge storage electrode material is then patterned using a charge storage electrode mask, thereby forming charge storage electrodes 42. Thereafter, the formation of a capacitor dielectric film 45 and a conductive layer 47 adapted to form plate electrodes is carried out.
Thereafter, a fourth interlayer insulating film 49 is formed on the resulting structure.
As shown in FIG. 1, in the semiconductor device, a step is defined between the memory cell region B formed with capacitors and the logic circuit region A formed with a logic circuit due to an increased stack height of the capacitor structure. Due to such a step or topology, it is impossible to form an accurate pattern in the logic circuit region A or memory cell region B. This is because when a particular layer formed on the capacitor structure is patterned in accordance with a photolithography process, there is a focus depth difference between exposure light onto the logic circuit region A and exposure light onto the memory cell region B. As a result, it is very difficult to form fine metal lines.
The present invention has been made in view of the above mentioned problems, and an object of the invention is to provide a method for fabricating a semiconductor device, in which dummy plate electrodes and charge storage electrodes are formed at a logic circuit region in the procedure for forming capacitors, thereby preventing the formation of a step between a logic circuit region and a memory cell region, and thus, allowing a formation of fine interconnection lines.
In accordance with the present invention, this object is accomplished by providing A method for fabricating a semiconductor device including a plurality of stacked capacitors on a semiconductor substrate having a logic circuit region and a memory cell region, wherein dummy plate electrodes and charge storage electrodes, each of which has the same height as that of the stacked capacitor, are formed at the logic circuit region when the stacked capacitor are formed at the memory cell region.
Preferably, this method comprises the steps of forming gate electrodes, source electrodes, and drain electrodes on the semiconductor substrate, and forming a first interlayer insulating film in a planarized fashion over an upper surface of a structure resulting from the formation of the electrodes, forming, on the first interlayer insulating film at the memory cell region, bit lines connected to the source electrodes while forming, on the first interlayer insulating film at the logic circuit region, first interconnection lines connected to the source, drain, and gate electrodes, and forming a second interlayer insulating film in a planarized fashion over an upper surface of a structure resulting from the formation of the bit lines and the first interconnection lines, forming contact holes at the first interconnection lines in the logic circuit region, forming a conductive material in a planarized fashion over an upper surface of a structure resulting from the formation of the contact holes, and etching back the conductive material, thereby forming contact plugs respectively connected to the first interconnection lines, forming an etch barrier film over an upper surface of a structure resulting from the formation of the contact plugs, forming contact holes exposing the drain electrodes, and forming a conductive material, adapted to form charge storage electrodes, over an upper surface of a structure resulting from the formation of the contact holes exposing the drain electrodes, patterning the charge storage electrode conductive material using a charge storage electrode mask, thereby forming the charge storage electrodes and the dummy charge storage electrodes, forming a capacitor dielectric film over an upper surface of a structure resulting from the formation of the charge storage electrodes and the dummy charge storage electrodes, and forming, over the capacitor dielectric film, a conductive material adapted to form plate electrodes, patterning the plate electrode conductive material using a plate electrode mask, thereby forming plate electrodes and dummy plate electrodes, and forming a third interlayer insulating film in a planarized fashion over an upper surface of a structure resulting from the formation of the plate electrodes and dummy plate electrodes, and forming second interconnection lines connected to the contact plugs formed at the first interconnection lines.